<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>Journals:- (Total : 15)</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size: 14px;">Sadulla Shaik, K. Sri Rama Krishna, Mazhar A, Munir A and Dinesh.M, &ldquo;Applying several soft computing techniques for prediction of bearing capacity of driven piles,&rdquo; Engineering&nbsp; with Computers, Springer, Vol. 34, No.130, pp. 1-12, 2019.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <strong><span style="color:#ff0000;">SCI (Impact Factor: 1.951)</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, Anil Kumar Kurra, and A. Surendar, &ldquo;A Novel High Secure Buffer based &nbsp;Physical Unclonable Functions (PUF&rsquo;s) for Device Authentication,&rdquo; Journal of Telecommunication Computing Electronics and Control (TELKOMNIKA), Vol. 17, No. 1, pp. 377-383, 2019.&nbsp; <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">A. Surendar and Sadulla Shaik, &ldquo;State level attribute compliance measure based efficient access restriction improved security in cloud environment&rdquo; Indonesian Journal of Electrical Engineering and Informatics (IJEEI), Vol. 7, No. 1, pp. 22-27, 2019. <strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">A. Surendar, Sadulla Shaik, Ali Noory Fajer, Mazhar Abbas and Meysam Najafi, &ldquo;Anti-inflammatory activity of&nbsp; synthesized diarylpentenedione&nbsp; derivatives and their drug delivery&nbsp; with silicon-nanotube (7,7),&rdquo; Current Science, Vol. 116, No.3, Feb-2019, pp. 468-472&nbsp; SCI (Impact Factor: 0.883)</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, K. Sri Rama Krishna, and Ramesh Vaddi, &ldquo;Nano-Scale Transistors with Circuit Interaction for Designing Energy- Efficient and Reliable Adder Cells at Low VDD IETE Technical Review (Taylor &amp; Francis), Vol. 35, No. 5, pp. 456&ndash;466, 2018.&nbsp; DOI: 10.1080/02564602.2017.1327826. SCI Expanded (Impact Factor: 1.34)</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, Anil Kumar Kurra, and A. Surendar, &ldquo;Statistical Analysis of Reliable Secure Transmission Gate Based Arbiter Physical Unclonable Functions (PUFs International Journal of Simulation: Systems, Science &amp; Technology (IJSSST), Vol. 19, No. 4,&nbsp; pp-6.1-6.6, 2018.&nbsp; DOI 10.5013/IJSSST.a.19.04.06.&nbsp;<strong><span style="color:#ff0000;"> Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">P. C. Shaker, Shaik Sadulla, B. Vinaya, &ldquo;Various Standard Image Filtering Methods Image Fusion Technique For Impulse Noise Removal From The Digital Image,&rdquo; Journal of &nbsp;Advanced Research in Dynamical &amp; Control Systems, Vol. 10, No. 9, pp.569-575, May-2018. <strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">A. Surendar, Shaik Sadulla, &ldquo;A Time Oriented Flow Inference Model Based on Low Rate&nbsp; DDoS Attack Detection for Improved Network Security,&rdquo; International Journal of Simulation:Systems, Science &amp; Technology (IJSSST), Vol. 19, No. 4, pp.7.1-7.5, May, 2018.DOI 10.5013/IJSSST.a.19.04.07 <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Hima Bindu Katikala and Sadulla Shaik, &ldquo;A Survey of the Vision Restoration Eye,&ldquo; Journal of International Pharmaceutical Research, Vol. 45, No. 1, pp. 501&ndash;505, November, 2018.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, K. Sri Rama Krishna, and Ramesh Vaddi, &ldquo;Tunnel Transistor-Based Reliable&nbsp; &nbsp;&nbsp;and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD,&rdquo; Journal of Circuits, Systems, and Computers (JCSC), Vol. 27, No. 3, pp. 1850046-(1&ndash;21), 2017. DOI: 10.1142/S0218126618500469&nbsp; <span style="color:#ff0000;"><strong>SCI Expanded (Impact Factor: 0.6)</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Sadulla Shaik, and K. Sri Rama Krishna, &ldquo;Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low VDD,&rdquo; Electronic Government, An International Journal (Inderscience),Vol.13, No.4, 2017.&nbsp;&nbsp; <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span>&nbsp;&nbsp; DOI: 10.1504/EG.2017.10006158</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Anil Kumar Kurra and Shaik Sadulla, &ldquo;Analysis of Physical Unclonable Functions (PUFs) For Secure Key Generation on Smartcard Chips,&rdquo; Journal of Advanced Research in&nbsp; &nbsp;Dynamical &amp; Control Systems, Vol. 9, No. 14, Feb, pp.1735-1745, 2017.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">A.Surendara, Sadulla Shaik and N.Usha Rani, &ldquo;Micro Sequence Identification of DNA Data &nbsp;&nbsp;Using Pattern Mining Techniques&rdquo;, Materials Today: Proceedings, Elsevier, Vol. 5, Iss. 1,pp. 578-587, 2017.&nbsp; &nbsp;<span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Gurugubelli Srirama Murthy, Darvinder Singh and Sadulla Shaik, &ldquo;An Area Efficient Built- &nbsp;In Redundancy Analysis for Embedded Memory with Selectable 1-D Redundancy&rdquo;&nbsp; Advances in Intelligent Systems and Computing, Springer International Publishing AG, DOI 10.1007/978-3-319-47952-1_58, 2016.&nbsp;&nbsp; &nbsp;<strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Sadulla Shaik, M. Pavan kumar, &nbsp;Prathiba Jonnala, G. B. V. Ramulu and Dr. K. Sri Rama &nbsp;&nbsp;&nbsp;Krishna. &ldquo;Design of a Cost-effective Wireless Patient Monitoring System Using &nbsp;&nbsp;PIC16F877A.&rdquo; International Journal of Applied Engineering Research,&nbsp; Vol. 10, No. 1, Print ISSN- 09734562, , pp. 380-383, 2015.&nbsp; <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Sk. Sadulla, Monisha A,&nbsp; V.V.S. Vijay Krishna and Prathiba J. &ldquo;FPGA Implementation of a Finite State Machine based Vending Machine&rdquo; International Journal of Systems , Algorithms &amp; Applications, Volume 3, Issue 13, ISSN Online: 2277-2677, June 2013.</span></li>
</ol>
<p style="text-align: justify;">
	&nbsp;</p>
<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>International Conferences:- (Total : 14)</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size: 14px;">Indira Y and Sadulla Shaik &ldquo;Performance Evaluation of Vedic Multiplier Using 180nm&nbsp;&nbsp;&nbsp;&nbsp; and FinFET Technology&rdquo; International Conference on Inventive Computing Systems and Applications, on Jan-29-30, 2018, Bangkok, Thailand.&nbsp;&nbsp;&nbsp; <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Aditya Japa, Sadulla Shaik and Ramesh Vaddi, &ldquo;Exploiting the Steep Subthreshold Slope&nbsp; Characteristics of Tunnel Transistors for Wide Tuning Range Voltage Controlled Ring Oscillator (VCRO) Design at Scaled Supply Voltages Down to 150mV&rdquo; 3rd International Conference on Emerging Electronics. On December 27-30, 2016 IIT Bombay, Mumbai, India. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, K Sri Rama Krishna, and Ramesh Vaddi, &ldquo;Tunnel Transistors with Circuit Co-Design in Designing Reliable Logic Gates for Energy Efficient Computing&rdquo; IEEE Asia Pacific Conference on Post Graduate Research in Microelectronics and Electronics (Prime Asia-2015). On 27th to 29th November 2015.&nbsp; &nbsp;&nbsp;<span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Sadulla Shaik, K Sri Rama Krishna, and Ramesh Vaddi, &ldquo;Circuit and Architectural Co-Design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing&rdquo; 29th International Conference on VLSI Design and 15th International Conference on Embedded System (VLSID-2016) On January 4-8 2016. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Bandreddy Siva Nageswara Rao, Sadulla Shaik, and Ramesh Vaddi, &ldquo;Design and Performance Benchmarking of Hetero-junction Tunnel FET based Differential Amplifier for Ultra-Low Power Applications.&rdquo; 28th IEEE International Conference on VLSI Design and 14th International Conference on Embedded Systems (VLSI Design &amp; ES-2015) <strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Gaurav Kaushal, K. Subramanyam, Siva Nageswar Rao, G.Vidya, Radhika Ramya, Sadulla Shaik H. Jeong, S. O. Jung, and Ramesh Vaddi. &ldquo;Design and Performance Benchmarking of Steep-Slope Tunnel Transistors for Low Voltage Digital and Analog Circuits Enabling Self-Powered SOCs.&rdquo; 11th International Soc Design Conference (ISOCC-2014).&nbsp;&nbsp;&nbsp; <strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Subramanyam, Kasturi, Sadulla Shaik, and Ramesh Vaddi. &quot;Tunnel FET based low voltage static vs dynamic logic families for energy efficiency.&quot; VLSI Design and Test, 18th International Symposium on VDAT-14. IEEE, 2014. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Vallabhaneni, Harshita, Aditya Japa, Sadulla Shaik, K. Rama Krishna, and Ramesh Vaddi. &quot;Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm.&quot; 2nd International Conference on Devices,Circuits and Systems (ICDCS), pp. 1-5. IEEE, 2014. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Vijayakumar, Ch, M. Pavan Kumar, S. Sivaji, Sk Sadulla, J. Prathiba, and K. Vijay Kumar. &quot;Sensors based automated wheelchair.&quot; International Conference on Green Computing, Communication and Conservation of Energy (ICGCE), pp. 439-443. IEEE, 2013. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Shaik, Sadulla, and Prathiba Jonnala. &quot;Performance evaluation of different SRAM topologies using 180, 90 and 45 nm technology.&quot; International Conference on Renewable Energy and Sustainable Energy (ICRESE),. IEEE, 2013.&nbsp;&nbsp; <strong><span style="color:#ff0000;">Scopus Indexed</span></strong></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Jonnala, Prathiba, and Sadulla Shaik. &quot;Wireless solution for polyhouse cultivation using embedded system.&quot; International Conference on Renewable Energy and Sustainable Energy (ICRESE),. IEEE, 2013.<span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Sk Sadulla, Krishna, V.V.S.Vijay, A.Monisha, and J.Prathiba. &quot;Design and implementation of an automatic beverages vending machine and its performance evaluation using Xilinx ISE and Cadence.&quot; 4th International Conference on Computing, Communications and Networking Technologies (ICCCNT), pp. 1-6. IEEE, 2013. <span style="color:#ff0000;"><strong>Scopus Indexed</strong></span></span></li>
</ol>
<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>National Conferences:- (Total : 02)</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size:14px;">A.V.NageswaraRao, G.S.R.Satyanarayna and Shaik Sadulla, &ldquo;PSoC Based Wireless Biomedical Monitoring System Using RF&rdquo; National Conference on VLSI, Signal Processing &amp; Communications (NCVSComs-12), 2012.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Shaik Sadulla, &ldquo;Design &amp; Implementation of ARM7TDMI Based Biometric Reader&rdquo; National Level Conference on Advances in Computer and Communication (NCACC-05), 2005.</span></li>
</ol>
<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>Workshops/Seminars:</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated Electronics &amp; ICT Academy IIT Guwahati, Assam Sponsored one week Faculty Development Programme (FDP) on &ldquo;VLSI Design at Deep Submicron Node&rdquo; organized by Department of Electronics and Communication Engineering,&nbsp; PSG College of Technology at Coimbatore, on 4th to 8th February 2019.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated Electronics &amp; ICT Academy NIT, Warangal Sponsored one week Faculty Development Programme (FDP) on &ldquo;CMOS Analog IC Design&rdquo; organized by Department of Electronics and Communication Engineering, Velagapudi Ramakrishna Siddhartha Engineering College at Vijayawada on 13th to 18th November 2017.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated in AICTE Sponsored one week short term course on &ldquo;MOSFETs and Beyond&rdquo; organized by Department of Electrical Engineering IIT Madras, on 10th to 15th July 15 2017.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated in the National Level one week FDP on &ldquo;Ansys HFSS and 3d printing&rdquo; organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, on 17th to 23rd November 2016.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated in the National Level a three day&nbsp; workshop on &ldquo;Signal processing and communication using MATLA&rdquo; organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, held on 14th to 16th November 2016.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated a three day workshop on &ldquo;Bio-Signal Processing &amp; Measurements and Computing Everywhere&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, on 26th to 29th November 2015.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated a two day workshop on &ldquo;Recent Trends in Communication Technologies &amp; Signal Processing&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, on 27th to 28th September 2014.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated a three day workshop on &ldquo;VLSI Design Using Cadence Tool&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, on 9th to 11th June 2014.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Attended a two day workshop on &ldquo;System Design Using Xilinx FPGAs&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, on 9th to 10th July 2013.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated ISTE Sponsored Two-Week Workshop on &ldquo;Analog Electronics&rdquo; Organized by Department of Electronics and Communication Engineering, at NIT Warangal, held on 4th to 14th June 2013.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;Participated IUCEE Sponsored a five day Workshop on &ldquo;FPGA based Digital &amp; Embedded System Design&rdquo; &ldquo;Analog Electronics&rdquo; Organized by Department of Electronics and Communication Engineering at Vignan University, Vadlamudi, Guntur, on 26th to 30th June 2012.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Attended a two day seminar on &ldquo;VLSI Design&rdquo; Organized by Department of Electronics and Communication Engineering at Vignan University, Vadlamudi, Guntur, on 6th to 7th February 2012.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Attended a one day seminar on &ldquo;RF System Design &amp; Testing&rdquo; Organized by Department of Electronics and Communication Engineering, at Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, held on 18th December, 2011.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated IUCEE Sponsored a five day Workshop on &ldquo;Advanced Signal Processing&rdquo; Organized by Department of Electronics and Communication Engineering, at at Vignan University, Vadlamudi, Guntur, held on 18th to 22nd July, 2011.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Attended a two day workshop on &ldquo;Image Processing and Cloud Computing&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan University, Vadlamudi, Guntur, held on 27th to 28th November, 2009.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Participated Two-Week Workshop on &ldquo;Comprehensive Course on Embedded System Design&rdquo; Organized by Department of Electronics and Communication Engineering, at Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, held on 15th to 27th June 2009.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Attended a two day workshop on &ldquo;Communications and Signal Processing- A Research Perspective&rdquo; Organized by Department of Electronics and Communication Engineering, at Vignan&rsquo;s Engineering College Vadlamudi, Guntur, held on 28th to 29th June, 2008.</span></li>
</ol>
<p style="text-align: justify;">
	&nbsp;</p>
<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>Academics and Administration:</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Pass percentage in every subject always&nbsp;&nbsp; : 90% - 95%.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Feedback analysis always&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 85% - 95%.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Department Level T&amp;P Coordinator&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 2017 - 2018, (82.82% Students got Placement).</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Department Level R&amp;D Coordinator&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 2016 - 2017.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Incharge HoD for about two months&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : September &amp; October-2016</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Department Level Academics and Attendance Coordinator: 2014 - 2016.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Central level discipline coordinator&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 2008 - 2014.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Coordinator for Workshops, Seminars, Guest Lectures and Conferences : 2008 - 2014.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Organized National Conferences&nbsp; : 02</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Organized Workshops&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 18 (For Faculty/Students).</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Organized Seminars&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 05 (For Students).</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Organized Guest Lectures&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; : 06 (For Students).</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Counselor for 2007-2011, 2011-2015 and 2014-2018 Batch students.</span></li>
</ol>
<p style="text-align: justify;">
	<span style="font-size:16px;"><strong>Honors and Awards:-</strong></span></p>
<ol>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Session Chair for International Conference on Technological Emerging Challenges</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">&nbsp;(ICTEC-19), 15 &amp; 16th, March 2019, at Tirumala Engineering College, Narasaraopet, Andhra &nbsp;Pradesh.</span></li>
	<li style="text-align: justify;">
		&nbsp;</li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Keynote Speech on Nano-Sclae Transistors in International Conference on Inventive Computing Systems and Applications, on Jan-29, 2018, at Bangkok, Thailand.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Star Performer based on Research, Academic, Administrative and Student feedback for&nbsp; the academic year 2016-2017, Vignan&rsquo;s Foundation for Science, Technology &amp; Research, 2017.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Won Bronze Leaf Certificate in IEEE Asia-Pacific Conference on Postgraduate Research in Microelectronics &amp; Electronics, 2015.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Won Runner-Up Prize in design contest at 28th IEEE International Conference on VLSI &nbsp;Design and 14th International Conference on Embedded Systems (VLSID &amp; ES-2015), Bangalore, 2015.</span></li>
	<li style="text-align: justify;">
		<span style="font-size:14px;">Best Performing Employee in the AAC-13, 2013.</span></li>
</ol>
<p style="text-align: justify;">
	&nbsp;</p>
<p style="margin-left:9.0pt;">
	&nbsp;</p>
